Standard Library -- Signal
VectorSaturation

  
Description:   The Vector Saturation component limits the input signal using the upper and lower limits on an element by element basis such that

If(SigIn[I]>UpperLimit[I]): SigOut[I] = UpperLimit[I]

If(SigIn[I]<LowerLimit[I]): SigOut[I] = LowerLimit[I]

Otherwise: SigOut[I] = SigIn[I]
 

Inputs:   SimRealVar SigIn[DIMA] – Input Signal (ND)
SimRealVar UpperLimit[DIMA] – Upper Limit (ND)
SimRealVar LowerLimit[DIMA] – Lower Limit (ND)
 
Outputs:   SimRealVar SigOut[DIMA] – Saturated Output Signal
 
States:   None
 
Dimensions:   DIMA – Sets the width of input, and output vectors
 
 

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